At the 2026 CIOE China Optics Expo, AI interconnect emerged as the hottest topic. Astera Labs, a typical representative, has seen its product value per accelerator surge from under $100 to several thousand dollars, reflecting how AI’s computational expansion reshapes the underlying interconnect architecture.
Three-Stage Value Leap for Interconnect Products
Founded in 2017, Astera Labs initially entered the high-speed interconnect market with PCIe Retimers. As AI evolved, its product line expanded to copper interconnect, optical interconnect, and rack-level interconnect systems. The value trajectory is clear:
- Early stage (Aries series): Product value per accelerator under $100
- Mid stage (with switching chips and memory): Value rose to hundreds of dollars
- Current (scale-up switch phase): Value per accelerator has reached several thousand dollars
The company originally expected Scorpio series to become the primary revenue source in Q4 2026, but this milestone has been brought forward to Q3.
Copper-Optical Boundary Reconstructed: Rate and Scale as Key Variables
Traditional understanding—copper for short distances, optical for long—is challenged in the AI era. Distance is no longer the decisive factor, Sanjay Gajendra, President and COO of Astera Labs, stated. The core determinants for when to transition to optical within racks are transmission rate and GPU scale.
Specifically:
- 200G/lane connections: Copper interconnect remains viable
- 400G/lane and above: Optical interconnect accelerates into rack interior
Scale effects intensify the shift: when systems expand to thousands of GPUs across racks, customers evaluate solutions by system-wide unit Token cost. Taking NVIDIA’s NVL72 (72-GPU scale-up domain) as reference, larger scale-up domains can reduce data frequently traversing scale-out networks, avoiding additional latency and complexity. This gives optical interconnect a cost advantage in expanding scale-up scale.
On the technology front, Gajendra forecasts NPO (Near-Package Optics) will enter scale-up deployment around 2027; CPO (Co-Packaged Optics), currently limited to small-scale applications, may not see wider scale-up deployment until 2029-2030.
Sino-US Market Divergence Emerges
Customization is intensifying, but external interfaces uphold open standards. Gajendra contrasts Sino-US markets:
- North America: Dominated by Amazon, Microsoft, Google, and Meta, emphasizing standardization, supply chain reuse, and cross-generation compatibility
- China: Beyond ByteDance, Alibaba, and others, numerous startups enter the space, demanding faster supplier response and deployment speed
While internal systems grow increasingly customized, external interconnect interfaces standardize. For instance, ByteDance’s infrastructure focuses on in-house services, whereas Alibaba supports both internal applications and external cloud clients, diverging their processor and server designs.
Inference Market: Decentralization Opens New Opportunities
Gajendra notes that while inference and training share high bandwidth, low latency, and low power needs, priorities differ: training emphasizes computational power, while inference prioritizes memory and latency. More crucially, the inference market’s participants and system forms are far more decentralized than training.
This means interconnect demand no longer hinges solely on a few hyperscalers’ training cluster expansions. More diverse systems—different scales and deployment models—will emerge, requiring interconnect vendors to adapt to increasingly heterogeneous requirements.
Practical Recommendations
- If building large GPU training clusters (hundreds of GPUs+), evaluate scale-up architecture with optical interconnect to optimize Token cost
- If in early inference or smaller-scale deployments, copper interconnect remains cost-effective; no need to adopt cutting-edge optical yet
Final Thoughts
Interconnect has evolved from a supporting role to a core variable in AI infrastructure design. When connection methods dictate GPU scale, system latency, and Token cost, their value extends beyond data transmission to determining whether raw compute turns into usable performance.